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MAXIM - DS1021, DS1021-25, DS1021-50 Programmable 8 bit Silicon Delay Line - Delay Lines and Counters DS1021, DS1021-25, DS1021-50

DS1021, DS1021-25, DS1021-50 Programmable 8 bit Silicon Delay Line 此图片只做参考用
真图请以实物为准
库存状况
  • 库存数量: 2009
  • 包装规格:
  • 最小订单量:1
  • 多重订单量:1
  • 单位价格(不含税):CNY 54.00
数量:
价格
    数量单位价格(不含税)
    1-24CNY 54.00
    25-49CNY 51.30
    50-99CNY 48.60
    100-249CNY 45.90
  • 制造商:MAXIM
  • 库存编号:1616237
  • 商品型号:DS1021S-50
  • RoHS胁从产品:
  • 备注:
  • 产品描述:The DS1021 is an 8-bit programmable delay line that reproduces an input logic state at the output after a user-programmed delay.
The DS1021 is an 8-bit programmable delay line that reproduces an input logic state at the output after a user-programmed delay. It is similar to the DS1020 but with the economy of reduced specifications. Available in two versions, total delays are varied over 256 steps and range from an inherent 10ns minimum delay in both versions to a maximum delay of 137.5ns. The DS1021 can be programmed over the 3-wire serial port or the 8-pin parallel port. The DS1021 is TTL- and CMOS-compatible and capable of driving up to ten 74LS-type loads. Both leading- and trailing-edge accuracy are specified.

The DS1021 is an effective, economical solution to the designer working with the complex timing requirements of mismatched ASICs or other components, or with the strict timing tolerances of increasing system clock rates. With the DS1021's programmable outputs, the user can precisely adjust timing to application needs and improve system performance. Innovative circuit designs and factory laser or EPROM trimming enhance accuracy without the need for external components, saving cost and space.

Key Features

  • All-silicon time delay
  • Models with 0.25ns and 0.5ns steps
  • Programmable using 3-wire serial port or 8-bit parallel port
  • Leading and trailing edge accuracy
  • Auto-insertable, low profile
  • Low-power CMOS with TTL compatibility
  • Vapor phase, IR, and wave solderable
  
  

Diagram

DS1021, DS1021-25, DS1021-50: Functional Block Diagram
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